The circuit for ternary decoder, ternary logic gates (TNOR, TAND, TOR), ternary inverters (STI, PTI, NTI), and T-buffer are also designed. The present paper proposes a circuit for ternary to binary half adder using CMOS technology. Ternary logic devices are expected to offer a significant increase in information handling capability over binary logic systems. Ternary logic provides a good alternative to existing binary system logic in terms of reduced interconnects and higher operating speeds. Higher radix system is capable of reducing the number of wire interconnects. To further improve the packing density, researchers are looking for higher radix number system over aggressive device scaling. However, further reduction in minimum feature size of the transistors implementing binary-based digital systems is severely challenged by heat dissipation among other issues. The logic operations are performed using underlying transistor switching actions. Digital systems are designed using binary radix which works on two-valued logic popularly known as low (0) and high (1).
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